1. Technical Field
The present invention relates generally to a semiconductor integrated circuit, and more particularly, to a test circuit and method of testing a semiconductor integrated circuit.
2. Related Art
A three-dimensional (3D) semiconductor integrated circuit formed by, for example, packaging a plurality of stacked chips into a single package is one form of elevating the degree of integration to a higher level. By stacking two or more chips over each other vertically, the 3D semiconductor integrated circuit can achieve a high degree of integration in a given space.
There are various schemes for realizing a 3D semiconductor integrated circuit. In one scheme, a plurality of the structurally same chips are stacked, and the stacked chips are coupled to each other by wires such as metal lines, so as to allow the stacked chips to operate as a single semiconductor integrated circuit.
In a through-silicon via (TSV) type semiconductor apparatus, silicon vias are formed through a plurality of stacked chips so that all the chips can be electrically connected to each other through the silicon vias instead of the metal lines. In the TSV type semiconductor apparatus, since the chips are electrically connected to each other through the silicon vias vertically passing through the chips, it is possible to further reduce the area of a package, as compared to a semiconductor integrated circuit in which the chips are electrically connected to each other through bonding wirings bonded adjacent to the edges of the chips.
The TSVs are formed generally in a packaging process after which all chips stacked in parallel to each other can to be connected to each other. However, the TSVs may be formed in advance in the chip fabricating process in order to connect the stacked chips to one another. For example, as illustrated in FIG. 1, the TSVs are formed in advance in a chip fabricating process such that the TSVs of the first and second chips are coupled to the internal circuits of the first and second chips respectively. Then, in a packaging process, while the first chip and the second chip are stacked, the TSV of the first chip is coupled to the internal circuit of the second chip through a bump, so that a serial connection can be achieved in the following sequence of: the internal circuit of the first chip, the TSV of the first chip, the internal circuit of the second chip, and the TSV of the second chip.
A current leakage test is mainly used for determining whether the TSVs are formed normally. In general, a test is performed after a plurality of chips are stacked and packaged. However, since the TSVs for the serial or parallel connection can be formed in a chip fabricating process as described above, it is necessary to perform a test for determining whether the TSVs have been normally formed in a wafer level.